module	hub_test_data(
	input	wire		sclk,
	input	wire		resetb,
	
	input	wire		time_1ms_sync,
	output	reg	[11:0]	left_hub,
	input	wire	[11:0]	right_hub,
	
	output	wire	[11:0]	hub_test_result
);
parameter	DIV_NUM=255;
reg	[8:0]	div_cnt;

reg	[7:0]	ms_cnt;
reg	[11:0]	hub_result_current;
wire		test_start;
reg	[11:0]	right_hub_t;
reg		hub_re_0,hub_re_1,hub_re_2,hub_re_3,hub_re_4,hub_re_5,hub_re_6,hub_re_7,hub_re_8,hub_re_9,hub_re_10,hub_re_11;

always @(posedge sclk or negedge resetb)
	if(resetb==1'b0)
		ms_cnt<='d0;
	else if(time_1ms_sync==1 && ms_cnt[7]==0)
		ms_cnt<=ms_cnt+1;

assign	test_start=ms_cnt[7];

always @(posedge sclk or negedge resetb)
	if(resetb==1'b0)
		div_cnt<='d0;
	else if(test_start==1)
	begin
		if(div_cnt>=DIV_NUM)
			div_cnt<='d0;
		else
			div_cnt<=div_cnt+1'b1;
	end
	else
		div_cnt<='d0;
		
always @(posedge sclk or negedge resetb)
	if(resetb==1'b0)
		left_hub<=0;
	else if(div_cnt==DIV_NUM-1)
		left_hub<=left_hub+1;

always @(posedge sclk)
	right_hub_t<=right_hub;
		
always @(posedge sclk or negedge resetb)
	if(resetb==1'b0)
		hub_result_current<=0;
	else if(div_cnt==DIV_NUM-32)
		hub_result_current<=left_hub ^ right_hub_t;

always @(posedge sclk or negedge resetb)
	if(resetb==1'b0)
		hub_re_0<=0;
	else if(div_cnt==DIV_NUM-64 && hub_result_current[0]!=0)
		hub_re_0<=hub_result_current[0];

always @(posedge sclk or negedge resetb)
	if(resetb==1'b0)
		hub_re_1<=0;
	else if(div_cnt==DIV_NUM-64 && hub_result_current[1]!=0)
		hub_re_1<=hub_result_current[1];

always @(posedge sclk or negedge resetb)
	if(resetb==1'b0)
		hub_re_2<=0;
	else if(div_cnt==DIV_NUM-64 && hub_result_current[2]!=0)
		hub_re_2<=hub_result_current[2];

always @(posedge sclk or negedge resetb)
	if(resetb==1'b0)
		hub_re_3<=0;
	else if(div_cnt==DIV_NUM-64 && hub_result_current[3]!=0)
		hub_re_3<=hub_result_current[3];

always @(posedge sclk or negedge resetb)
	if(resetb==1'b0)
		hub_re_4<=0;
	else if(div_cnt==DIV_NUM-64 && hub_result_current[4]!=0)
		hub_re_4<=hub_result_current[4];

always @(posedge sclk or negedge resetb)
	if(resetb==1'b0)
		hub_re_5<=0;
	else if(div_cnt==DIV_NUM-64 && hub_result_current[5]!=0)
		hub_re_5<=hub_result_current[5];

always @(posedge sclk or negedge resetb)
	if(resetb==1'b0)
		hub_re_6<=0;
	else if(div_cnt==DIV_NUM-64 && hub_result_current[6]!=0)
		hub_re_6<=hub_result_current[6];

always @(posedge sclk or negedge resetb)
	if(resetb==1'b0)
		hub_re_7<=0;
	else if(div_cnt==DIV_NUM-64 && hub_result_current[7]!=0)
		hub_re_7<=hub_result_current[7];

always @(posedge sclk or negedge resetb)
	if(resetb==1'b0)
		hub_re_8<=0;
	else if(div_cnt==DIV_NUM-64 && hub_result_current[8]!=0)
		hub_re_8<=hub_result_current[8];

always @(posedge sclk or negedge resetb)
	if(resetb==1'b0)
		hub_re_9<=0;
	else if(div_cnt==DIV_NUM-64 && hub_result_current[9]!=0)
		hub_re_9<=hub_result_current[9];

always @(posedge sclk or negedge resetb)
	if(resetb==1'b0)
		hub_re_10<=0;
	else if(div_cnt==DIV_NUM-64 && hub_result_current[10]!=0)
		hub_re_10<=hub_result_current[10];	

always @(posedge sclk or negedge resetb)
	if(resetb==1'b0)
		hub_re_11<=0;
	else if(div_cnt==DIV_NUM-64 && hub_result_current[11]!=0)
		hub_re_11<=hub_result_current[11];	
		
assign	hub_test_result={hub_re_11,hub_re_10,hub_re_9,hub_re_8,hub_re_7,hub_re_6,hub_re_5,hub_re_4,hub_re_3,hub_re_2,hub_re_1,hub_re_0};
endmodule